Multi-Cycle ALU¶
Ch 12
ALU — Arithmetic Logic Unit |
**Group:** Multi-Cycle ALU |
**Forms:** 28 |
**Unique mnemonics:** 28
Multi-cycle ALU operations: division, remainder, and extended multiply.
Instructions¶
| Mnemonic | Assembly | Length | Decode | Description |
|---|---|---|---|---|
| DIV | div SrcL, SrcR, ->{t, u, Rd} |
32 | — | Signed integer division. |
| DIVU | divu SrcL, SrcR, ->{t, u, Rd} |
32 | — | Unsigned integer division. |
| DIVUW | divuw SrcL, SrcR, ->{t, u, Rd} |
32 | — | 32-bit word unsigned integer division. |
| DIVW | divw SrcL, SrcR, ->{t, u, Rd} |
32 | — | 32-bit word signed integer division. |
| HL.DIV | hl.div SrcL, SrcR, ->Dst0, Dst1 |
48 | — | [48-bit HL.] Signed integer division. |
| HL.DIVU | hl.divu SrcL, SrcR, ->Dst0, Dst1 |
48 | — | [48-bit HL.] Unsigned integer division. |
| HL.DIVUW | hl.divuw SrcL, SrcR, ->Dst0, Dst1 |
48 | — | [48-bit HL.] Instruction from the Multi-Cycle ALU group. |
| HL.DIVW | hl.divw SrcL, SrcR, ->Dst0, Dst1 |
48 | — | [48-bit HL.] Instruction from the Multi-Cycle ALU group. |
| HL.MADD | hl.madd SrcL, SrcR, SrcD, ->Dst0, Dst1 |
48 | — | [48-bit HL.] Instruction from the Multi-Cycle ALU group. |
| HL.MADDW | hl.maddw SrcL, SrcR, SrcD, ->Dst0, Dst1 |
48 | — | [48-bit HL.] Instruction from the Multi-Cycle ALU group. |
| HL.MUL | hl.mul SrcL, SrcR, ->Dst0, Dst1 |
48 | — | [48-bit HL.] Integer multiply. |
| HL.MULU | hl.mulu SrcL, SrcR, ->Dst0, Dst1 |
48 | — | [48-bit HL.] Instruction from the Multi-Cycle ALU group. |
| HL.REM | hl.rem SrcL, SrcR, ->Dst0, Dst1 |
48 | — | [48-bit HL.] Signed integer remainder. |
| HL.REMU | hl.remu SrcL, SrcR, ->Dst0, Dst1 |
48 | — | [48-bit HL.] Unsigned integer remainder. |
| HL.REMUW | hl.remuw SrcL, SrcR, ->Dst0, Dst1 |
48 | — | [48-bit HL.] Instruction from the Multi-Cycle ALU group. |
| HL.REMW | hl.remw SrcL, SrcR, ->Dst0, Dst1 |
48 | — | [48-bit HL.] Instruction from the Multi-Cycle ALU group. |
| MADD | madd SrcL, SrcR, SrcD, ->{t, u, Rd} |
32 | — | Multiply-add: Dest = SrcD + SrcL * SrcR. |
| MADDW | maddw SrcL, SrcR, SrcD, ->{t, u, Rd} |
32 | — | 32-bit word multiply-add. |
| MUL | mul SrcL, SrcR, ->{t, u, Rd} |
32 | — | Integer multiply (lower product written to destination). |
| MULU | mulu SrcL, SrcR, ->{t, u, Rd} |
32 | — | Integer multiply (unsigned). |
| MULUW | muluw SrcL, SrcR, ->{t, u, Rd} |
32 | — | 32-bit word integer multiply (unsigned). |
| MULW | mulw SrcL, SrcR, ->{t, u, Rd} |
32 | — | 32-bit word integer multiply. |
| REM | rem SrcL, SrcR, ->{t, u, Rd} |
32 | — | Signed integer remainder. |
| REMU | remu SrcL, SrcR, ->{t, u, Rd} |
32 | — | Unsigned integer remainder. |
| REMUW | remuw SrcL, SrcR, ->{t, u, Rd} |
32 | — | 32-bit word unsigned remainder. |
| REMW | remw SrcL, SrcR, ->{t, u, Rd} |
32 | — | 32-bit word signed remainder. |
| V.MADD | v.madd SrcL, SrcR, SrcD, ->Dst |
64 | — | [64-bit V.] Instruction from the Multi-Cycle ALU group. |
| V.MUL | v.mul SrcL, SrcR, ->Dst |
64 | — | [64-bit V.] Integer multiply. |