DIVW

32-bit Base **Group:** Multi-Cycle ALU  |  Ch 12   ALU — Arithmetic Logic Unit  |  **Length:** 32  |  **Decode:** —

Assembly Syntax

• divw SrcL, SrcR, ->{t, u, Rd}

Encoding

Bitfield encoding diagram. MSB is on the left, LSB on the right.

Description

32-bit word signed integer division.

Pseudocode (informative)

// Execute DIVW as defined by the Multi-Cycle ALU semantics.

Encoding Notes

No additional encoding notes.

Full Catalog Forms

Assembly	Length	Decode
divw SrcL, SrcR, ->{t, u, Rd}	32	—

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