Instruction Groups¶
Alphabetical list of all 69 instruction groups in the LinxISA v0.58.0 catalog. See the chapter index for the manual organization.
| Group | Forms | Chapter | Sample mnemonics |
|---|---|---|---|
| Execution Control | 10 | Ch 19 — source | ACRC, ACRE, ASSERT, BSE, BWE, BWI, BWT, EBREAK +2 |
| Arithmetic Operation 64bit | 21 | Ch 12 — source | ADD, ADDI, AND, ANDI, HL.ADDI, HL.ANDI, HL.ORI, HL.SUBI +13 |
| Arithmetic Operation 32bit | 21 | Ch 12 — source | ADDIW, ADDW, ANDIW, ANDW, HL.ADDIW, HL.ANDIW, HL.ORIW, HL.SUBIW +13 |
| PC-Relative | 4 | Ch 16 — source | ADDTPC, HL.ADDTPC, HL.SETRET, SETRET |
| Bundle Control Attribute | 1 | — | B.CATR |
| Bundle Data Attribute | 1 | — | B.DATR |
| Bundle Argument | 3 | — | B.DIM |
| Branch | 10 | Ch 16 — source | B.EQ, B.GE, B.GEU, B.LT, B.LTU, B.NE, B.NZ, B.Z +2 |
| Bundle Hint | 2 | — | B.HINT |
| Bundle Input & Output | 6 | — | B.IOR, B.IOT |
| Bundle Offset | 1 | — | B.TEXT |
| Cache Maintain | 16 | Ch 19 — source | BC.IALL, BC.IVA, DC.CISW, DC.CIVA, DC.CSW, DC.CVA, DC.IALL, DC.ISW +8 |
| Bit Operation | 8 | Ch 12 — source | BCNT, BIC, BIS, BXS, BXU, CLZ, CTZ, REV |
| Bundle Split | 60 | — | BSTART, BSTART.FP, BSTART.GMOV, BSTART.MGATHER, BSTART.MGATHER.CAS, BSTART.MGATHER.MASK, BSTART.MPAR, BSTART.MSCATTER +33 |
| BSTART | 20 | Ch 4 — source | BSTART CALL, HL.BSTART CALL, HL.BSTART.FP, HL.BSTART.STD, HL.BSTART.SYS, L.BSTART.FP, L.BSTART.STD, L.BSTART.SYS |
| Block Split | 2 | Ch 4 — source | BSTART.VPAR, BSTART.VSEQ |
| Arithmetic Operation | 20 | Ch 12 — source | C.ADD, C.AND, C.OR, C.SUB, V.ADD, V.ADDI, V.AND, V.ANDI +12 |
| Arithmetic | 1 | Ch 12 — source | C.ADDI |
| Bundle Dimension | 1 | — | C.B.DIMI |
| Bundle Shared Operand Binding | 1 | — | C.B.IOS |
| C.BSTART | 7 | Ch 15 — source | C.BSTART.FP, C.BSTART.MPAR, C.BSTART.MSEQ, C.BSTART.STD, C.BSTART.SYS, C.BSTART.VPAR, C.BSTART.VSEQ |
| C.TINST | 6 | Ch 19 — source | C.CMP.EQI, C.CMP.NEI, C.EBREAK, C.SLLI, C.SRLI, C.SSRGET |
| Load Immediate Offset | 23 | Ch 11 — source | C.LDI, C.LWI, LBI, LBUI, LDI, LHI, LHUI, LWI +15 |
| Move | 3 | Ch 12 — source | C.MOVI, C.MOVR, C.SETRET |
| Store Immediate Offset | 9 | Ch 11 — source | C.SDI, C.SWI, SBI, SDI, SDI.U, SHI, SHI.U, SWI +1 |
| Set Commit Argument | 26 | Ch 16 — source | C.SETC.EQ, C.SETC.NE, HL.SETC.ANDI, HL.SETC.EQI, HL.SETC.GEI, HL.SETC.GEUI, HL.SETC.LTI, HL.SETC.LTUI +18 |
| C.UNARY | 7 | Ch 12 — source | C.SETC.TGT, C.SEXT.B, C.SEXT.H, C.SEXT.W, C.ZEXT.B, C.ZEXT.H, C.ZEXT.W |
| Atomic Operation | 72 | Ch 14 — source | CASB, CASD, CASH, CASW, LD.ADD, LD.AND, LD.OR, LD.SMAX +64 |
| Compare Instruction | 40 | Ch 16 — source | CMP.AND, CMP.ANDI, CMP.EQ, CMP.EQI, CMP.GE, CMP.GEI, CMP.GEU, CMP.GEUI +32 |
| Compound Operation | 1 | Ch 12 — source | CSEL |
| Multi-Cycle ALU | 28 | Ch 12 — source | DIV, DIVU, DIVUW, DIVW, HL.DIV, HL.DIVU, HL.DIVUW, HL.DIVW +20 |
| DMA Operation | 1 | — | DMA |
| Floating-point Arithmetic | 12 | Ch 13 — source | FABS, FADD, FDIV, FEXP, FMADD, FMSUB, FMUL, FNMADD +4 |
| Format Convert | 12 | Ch 13 — source | FCVT, FCVTA, FCVTM, FCVTN, FCVTP, FCVTZ, SCVTF, UCVTF +4 |
| Floating-point Compare | 8 | Ch 13 — source | FEQ, FEQS, FGE, FGES, FLT, FLTS, FNE, FNES |
| Max-Min | 6 | Ch 16 — source | FMAX, FMIN, MAX, MAXU, MIN, MINU |
| RESERVE | 3 | Ch 18 — source | HL.BFI, HL.MIADD, HL.MISUB |
| Atomic | 4 | Ch 14 — source | HL.CASB, HL.CASD, HL.CASH, HL.CASW |
| Concat | 2 | Ch 18 — source | HL.CCAT, HL.CCATW |
| Load PC-Relative | 7 | Ch 11 — source | HL.LB.PCR, HL.LBU.PCR, HL.LD.PCR, HL.LH.PCR, HL.LHU.PCR, HL.LW.PCR, HL.LWU.PCR |
| Load Post-Index | 19 | Ch 11 — source | HL.LB.PO, HL.LBI.PO, HL.LBU.PO, HL.LBUI.PO, HL.LD.PO, HL.LDI.PO, HL.LDI.UPO, HL.LH.PO +11 |
| Load Pre-Index | 19 | Ch 11 — source | HL.LB.PR, HL.LBI.PR, HL.LBU.PR, HL.LBUI.PR, HL.LD.PR, HL.LDI.PR, HL.LDI.UPR, HL.LH.PR +11 |
| Load Long Offset | 12 | Ch 11 — source | HL.LBI, HL.LBUI, HL.LDI, HL.LDI.U, HL.LHI, HL.LHI.U, HL.LHUI, HL.LHUI.U +4 |
| Load Pair | 19 | Ch 11 — source | HL.LBIP, HL.LBP, HL.LBUIP, HL.LBUP, HL.LDIP, HL.LDIP.U, HL.LDP, HL.LHIP +11 |
| Long Immediate | 2 | Ch 12 — source | HL.LIS, HL.LIU |
| Immediate | 2 | Ch 12 — source | HL.LUI, LUI |
| Prefetch | 4 | Ch 11 — source | HL.PRF, HL.PRF.A, HL.PRFI.U, HL.PRFI.UA |
| General | 3 | Ch 4 — source | HL.QMT, HL.QPOP, HL.QPUSH |
| Store PC-Relative | 4 | Ch 11 — source | HL.SB.PCR, HL.SD.PCR, HL.SH.PCR, HL.SW.PCR |
| Store Post-Index | 14 | Ch 11 — source | HL.SB.PO, HL.SBI.PO, HL.SD.PO, HL.SD.UPO, HL.SDI.PO, HL.SDI.UPO, HL.SH.PO, HL.SH.UPO +6 |
| Store Pre-Index | 14 | Ch 11 — source | HL.SB.PR, HL.SBI.PR, HL.SD.PR, HL.SD.UPR, HL.SDI.PR, HL.SDI.UPR, HL.SH.PR, HL.SH.UPR +6 |
| Store Long Offset | 7 | Ch 11 — source | HL.SBI, HL.SDI, HL.SDI.U, HL.SHI, HL.SHI.U, HL.SWI, HL.SWI.U |
| Store Pair | 14 | Ch 11 — source | HL.SBIP, HL.SBP, HL.SDIP, HL.SDIP.U, HL.SDP, HL.SDP.U, HL.SHIP, HL.SHIP.U +6 |
| SSR Access | 7 | Ch 19 — source | HL.SSRGET, HL.SSRSET, LSRGET, SETC.TGT, SSRGET, SSRSET, SSRSWAP |
| Load Register Offset | 22 | Ch 11 — source | LB, LBU, LD, LH, LHU, LW, LWU, PRF +14 |
| Load Symbol | 7 | Ch 11 — source | LB.PCR, LBU.PCR, LD.PCR, LH.PCR, LHU.PCR, LW.PCR, LWU.PCR |
| Load UnScaled | 16 | Ch 11 — source | LDI.U, LHI.U, LHUI.U, LWI.U, LWUI.U, PRFI.U, V.LDI.U, V.LDI.U.BRG +8 |
| Store Register Offset | 21 | Ch 11 — source | SB, SD, SD.U, SH, SH.U, SW, SW.U, V.SB +13 |
| Store Symbol | 4 | Ch 11 — source | SB.PCR, SD.PCR, SH.PCR, SW.PCR |
| Bit Manipulation | 8 | Ch 12 — source | V.BCNT, V.BIC, V.BIS, V.BXS, V.BXU, V.CLZ, V.CTZ, V.REV |
| Three Source Integer | 2 | Ch 20 — source | V.CSEL, V.PSEL |
| Division | 2 | Ch 20 — source | V.DIV, V.REM |
| Floating Point Arithmetic | 5 | Ch 20 — source | V.FABS, V.FCLASS, V.FEXP, V.FRECIP, V.FSQRT |
| Three-Source Floating Point | 8 | Ch 20 — source | V.FADD, V.FDIV, V.FMADD, V.FMSUB, V.FMUL, V.FNMADD, V.FNMSUB, V.FSUB |
| Two-Source Floating Point | 12 | Ch 20 — source | V.FEQ, V.FEQS, V.FGE, V.FGES, V.FLT, V.FLTS, V.FMAX, V.FMIN +4 |
| General Manager | 2 | Ch 9 — source | V.QPOP, V.QPUSH |
| Reduce Operation with Register | 9 | Ch 20 — source | V.RDADD, V.RDAND, V.RDFADD, V.RDFMAX, V.RDFMIN, V.RDMAX, V.RDMIN, V.RDOR +1 |
| Store Offset | 14 | Ch 11 — source | V.SBI, V.SBI.BRG, V.SDI, V.SDI.BRG, V.SDI.U, V.SDI.U.BRG, V.SHI, V.SHI.BRG +6 |
| Shuffle | 8 | Ch 20 — source | V.SHFL.BFLY, V.SHFL.DOWN, V.SHFL.IDX, V.SHFL.UP, V.SHFLI.BFLY, V.SHFLI.DOWN, V.SHFLI.IDX, V.SHFLI.UP |