LinxISA v0.58 Architecture Contract

LinxISA v0.58 is the current stable hard-break profile. Its machine-readable authority is isa/v0.58/linxisa-v0.58.json together with the state and release artifacts under isa/v0.58/.

PTO alignment

The scalar, block, and tile surfaces match PTO ISA 0.58 exactly:

• 474 scalar forms;
• 99 command forms (74 CMD and 25 BBD);
• 109 tile operations (87 TEPL, 10 TLSU, and 12 CUBE).

The TLSU surface retains BSTART.MGATHER.MASK, BSTART.MSCATTER.MASK, and BSTART.MGATHER.CAS, with direct tile operations MGATHER_MASK, MSCATTER_MASK, and MGATHER_CAS.

isa/v0.58/pto-spec.lock.json pins the reviewed PTO source commit, tree, catalog hashes, release hash, encoding projection, and numeric profile.

Linx-only vector extension

Linx retains the additive two-level vector forms BSTART.VPAR, BSTART.VSEQ, C.BSTART.VPAR, C.BSTART.VSEQ, V.QPOP, and V.QPUSH. PTO ISA 0.58 reserves these six encodings but does not define their semantics.

Shared tile registers

Each core owns one bank of 256 Shared tile registers named S0 through S255. The names are absolute indices. The four PEs in the core may access every register in that bank; another core has a different bank.

C.B.IOS Sx binds a source and C.B.IOS -> Sx binds a destination. Shared writes atomically update descriptor and payload state. Reads do not update the descriptor. Uninitialized reads behave like reads of undefined registers.

An optional B.IOT 4-bit PE mask predicates fixed tile quarters. The absent mask is 0b1111, multiple set bits are legal, and zero is a NOP. The architecture specifies no inter-PE order beyond atomic read-modify-write; software must prevent conflicting accesses.

Version boundary

This release is a hard break from v0.57. Old command encodings and retired tile selectors are illegal. Toolchains must consume the v0.58 generated catalog and codecs; no old decode is part of the v0.58 architecture.