V.MUL

64-bit V. **Group:** Multi-Cycle ALU  |  Ch 12   ALU — Arithmetic Logic Unit  |  **Length:** 64  |  **Decode:** —

Assembly Syntax

• v.mul SrcL, SrcR, ->Dst

Encoding

Bitfield encoding diagram. MSB is on the left, LSB on the right.

Description

[64-bit V.] Integer multiply.

Pseudocode (informative)

rd = Trunc64(rs1 * rs2);

Encoding Notes

No additional encoding notes.

Full Catalog Forms

Assembly	Length	Decode
v.mul SrcL, SrcR, ->Dst	64	—

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