Arithmetic Operation 64bit¶
Ch 12
ALU — Arithmetic Logic Unit |
**Group:** Arithmetic Operation 64bit |
**Forms:** 21 |
**Unique mnemonics:** 21
Full 64-bit integer arithmetic instructions.
Instructions¶
| Mnemonic | Assembly | Length | Decode | Description |
|---|---|---|---|---|
| ADD | add SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>, ->{t, u, Rd} |
32 | — | Integer addition. Writes the sum of two registers to the destination. |
| ADDI | addi SrcL, uimm, ->{t, u, Rd} |
32 | — | Integer add-immediate. Adds a sign-extended 12-bit immediate to a register. |
| AND | and SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} |
32 | — | Bitwise AND of two registers. |
| ANDI | andi SrcL, simm, ->{t, u, Rd} |
32 | — | Bitwise AND with an immediate. |
| HL.ADDI | hl.addi SrcL, uimm, ->{t, u, Rd} |
48 | — | [48-bit HL.] Instruction from the Arithmetic Operation 64bit group. |
| HL.ANDI | hl.andi SrcL, simm, ->{t, u, Rd} |
48 | — | [48-bit HL.] Instruction from the Arithmetic Operation 64bit group. |
| HL.ORI | hl.ori SrcL, simm, ->{t, u, Rd} |
48 | — | [48-bit HL.] Instruction from the Arithmetic Operation 64bit group. |
| HL.SUBI | hl.subi SrcL, uimm, ->{t, u, Rd} |
48 | — | [48-bit HL.] Instruction from the Arithmetic Operation 64bit group. |
| HL.XORI | hl.xori SrcL, simm, ->{t, u, Rd} |
48 | — | [48-bit HL.] Instruction from the Arithmetic Operation 64bit group. |
| OR | or SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} |
32 | — | Bitwise OR of two registers. |
| ORI | ori SrcL, simm, ->{t, u, Rd} |
32 | — | Bitwise OR with an immediate. |
| SLL | sll SrcL, SrcR, ->{t, u, Rd} |
32 | — | Logical left shift by the value in SrcR. |
| SLLI | slli SrcL, shamt, ->{t, u, Rd} |
32 | — | Logical left shift by an immediate amount. |
| SRA | sra SrcL, SrcR, ->{t, u, Rd} |
32 | — | Arithmetic right shift by the value in SrcR. |
| SRAI | srai SrcL, shamt, ->{t, u, Rd} |
32 | — | Arithmetic right shift by an immediate amount. |
| SRL | srl SrcL, SrcR, ->{t, u, Rd} |
32 | — | Logical right shift by the value in SrcR. |
| SRLI | srli SrcL, shamt, ->{t, u, Rd} |
32 | — | Logical right shift by an immediate amount. |
| SUB | sub SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>, ->{t, u, Rd} |
32 | — | Integer subtraction. |
| SUBI | subi SrcL, uimm, ->{t, u, Rd} |
32 | — | Instruction from the Arithmetic Operation 64bit group. |
| XOR | xor SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} |
32 | — | Bitwise XOR of two registers. |
| XORI | xori SrcL, simm, ->{t, u, Rd} |
32 | — | Bitwise XOR with an immediate. |