AND

32-bit Base **Group:** Arithmetic Operation 64bit  |  Ch 12   ALU — Arithmetic Logic Unit  |  **Length:** 32  |  **Decode:** —

Assembly Syntax

• and SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}

Encoding

Bitfield encoding diagram. MSB is on the left, LSB on the right.

Description

Bitwise AND of two registers.

Pseudocode (informative)

rd = rs1 & rs2;

Encoding Notes

No additional encoding notes.

Full Catalog Forms

Assembly	Length	Decode
and SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}	32	—

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