Store Register Offset¶
Ch 11
AGU — Address Generation Unit |
**Group:** Store Register Offset |
**Forms:** 21 |
**Unique mnemonics:** 21
Store instructions with register offsets.
Instructions¶
| Mnemonic | Assembly | Length | Decode | Description |
|---|---|---|---|---|
| SB | sb SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>] |
32 | — | Stores a register value to memory. |
| SD | sd SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<3] |
32 | — | Stores a register value to memory. |
| SD.U | sd.u SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>] |
32 | — | Stores a register value to memory. |
| SH | sh SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<1] |
32 | — | Stores a register value to memory. |
| SH.U | sh.u SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>] |
32 | — | Stores a register value to memory. |
| SW | sw SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<2] |
32 | — | Stores a register value to memory. |
| SW.U | sw.u SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>] |
32 | — | Stores a register value to memory. |
| V.SB | v.sb<.local> SrcD.<T1>, [SrcL, <lc0>, SrcR.<T2><<<shamt>] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SB.BRG | v.sb.brg<.local> SrcD.<T1>, [SrcL, <lc0>, SrcR.<T2><<<shamt>] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SD | v.sd<.local> SrcD.<T1>, [SrcL, <lc0<<3>, SrcR.<T2><<(3+shamt)] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SD.BRG | v.sd.brg<.local> SrcD.<T1>, [SrcL, <lc0<<3>, SrcR.<T2><<(3+shamt)] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SD.U | v.sd.u<.local> SrcD.<T1>, [SrcL, <lc0<<3>, SrcR.<T2><<<shamt>] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SD.U.BRG | v.sd.u.brg<.local> SrcD.<T1>, [SrcL, <lc0<<3>, SrcR.<T2><<<shamt>] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SH | v.sh<.local> SrcD.<T1>, [SrcL, <lc0<<1>, SrcR.<T2><<(1+shamt)] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SH.BRG | v.sh.brg<.local> SrcD.<T1>, [SrcL, <lc0<<1>, SrcR.<T2><<(1+shamt)] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SH.U | v.sh.u<.local> SrcD.<T1>, [SrcL, <lc0<<1>, SrcR.<T2><<<shamt>] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SH.U.BRG | v.sh.u.brg<.local> SrcD.<T1>, [SrcL, <lc0<<1>, SrcR.<T2><<<shamt>] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SW | v.sw<.local> SrcD.<T1>, [SrcL, <lc0<<2>, SrcR.<T2><<(2+shamt)] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SW.BRG | v.sw.brg<.local> SrcD.<T1>, [SrcL, <lc0<<2>, SrcR.<T2><<(2+shamt)] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SW.U | v.sw.u<.local> SrcD.<T1>, [SrcL, <lc0<<2>, SrcR.<T2><<<shamt>] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SW.U.BRG | v.sw.u.brg<.local> SrcD.<T1>, [SrcL, <lc0<<2>, SrcR.<T2><<<shamt>] |
64 | — | [64-bit V.] Stores a register value to memory. |