SW

32-bit Base **Group:** Store Register Offset  |  Ch 11   AGU — Address Generation Unit  |  **Length:** 32  |  **Decode:** —

Assembly Syntax

• sw SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<2]

Encoding

Bitfield encoding diagram. MSB is on the left, LSB on the right.

Description

Stores a register value to memory.

Pseudocode (informative)

Store(/* addr */, rs2);

Encoding Notes

No additional encoding notes.

Full Catalog Forms

Assembly	Length	Decode
sw SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<2]	32	—

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