Shuffle¶
Ch 20
VEC — Vector / SIMD Execution (lx64) |
**Group:** Shuffle |
**Forms:** 8 |
**Unique mnemonics:** 8
Vector lane shuffle operations.
Instructions¶
| Mnemonic | Assembly | Length | Decode | Description |
|---|---|---|---|---|
| V.SHFL.BFLY | v.shfl.bfly SrcL, SrcP, ->Dst |
64 | — | [64-bit V.] Instruction from the Shuffle group. |
| V.SHFL.DOWN | v.shfl.down SrcL, SrcR, SrcP, ->Dst |
64 | — | [64-bit V.] Instruction from the Shuffle group. |
| V.SHFL.IDX | v.shfl.idx SrcL, SrcR, SrcP, ->Dst |
64 | — | [64-bit V.] Instruction from the Shuffle group. |
| V.SHFL.UP | v.shfl.up SrcL, SrcR, SrcP, ->Dst |
64 | — | [64-bit V.] Instruction from the Shuffle group. |
| V.SHFLI.BFLY | v.shfli.bfly SrcL, imm, ->Dst |
64 | — | [64-bit V.] Instruction from the Shuffle group. |
| V.SHFLI.DOWN | v.shfli.down SrcL, SrcR, imm, ->Dst |
64 | — | [64-bit V.] Instruction from the Shuffle group. |
| V.SHFLI.IDX | v.shfli.idx SrcL, SrcR, imm, ->Dst |
64 | — | [64-bit V.] Instruction from the Shuffle group. |
| V.SHFLI.UP | v.shfli.up SrcL, SrcR, imm, ->Dst |
64 | — | [64-bit V.] Instruction from the Shuffle group. |