Reduce Operation with Register¶
Ch 20
VEC — Vector / SIMD Execution (lx64) |
**Group:** Reduce Operation with Register |
**Forms:** 9 |
**Unique mnemonics:** 9
Vector reduction operations.
Instructions¶
| Mnemonic | Assembly | Length | Decode | Description |
|---|---|---|---|---|
| V.RDADD | v.rdadd SrcL, ->Dst |
64 | — | [64-bit V.] Instruction from the Reduce Operation with Register group. |
| V.RDAND | v.rdand SrcL, ->Dst |
64 | — | [64-bit V.] Instruction from the Reduce Operation with Register group. |
| V.RDFADD | v.rdfadd SrcL, ->Dst |
64 | — | [64-bit V.] Instruction from the Reduce Operation with Register group. |
| V.RDFMAX | v.rdfmax SrcL, ->Dst |
64 | — | [64-bit V.] Instruction from the Reduce Operation with Register group. |
| V.RDFMIN | v.rdfmin SrcL, ->Dst |
64 | — | [64-bit V.] Instruction from the Reduce Operation with Register group. |
| V.RDMAX | v.rdmax SrcL, ->Dst |
64 | — | [64-bit V.] Instruction from the Reduce Operation with Register group. |
| V.RDMIN | v.rdmin SrcL, ->Dst |
64 | — | [64-bit V.] Instruction from the Reduce Operation with Register group. |
| V.RDOR | v.rdor SrcL, ->Dst |
64 | — | [64-bit V.] Instruction from the Reduce Operation with Register group. |
| V.RDXOR | v.rdxor SrcL, ->Dst |
64 | — | [64-bit V.] Instruction from the Reduce Operation with Register group. |