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V.RDFMIN

64-bit V. **Group:** Reduce Operation with Register  |  Ch 20   VEC — Vector / SIMD Execution (lx64)  |  **Length:** 64  |  **Decode:** —

Assembly Syntax

  • v.rdfmin SrcL, ->Dst

Encoding

V.RDFMIN encoding
Bitfield encoding diagram. MSB is on the left, LSB on the right.

Description

[64-bit V.] Instruction from the Reduce Operation with Register group.

Pseudocode (informative)

// Execute V.RDFMIN as defined by the Reduce Operation with Register semantics.

Encoding Notes

No additional encoding notes.

Full Catalog Forms

Assembly Length Decode
v.rdfmin SrcL, ->Dst 64 —
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