Execution Control¶
Ch 19
SYS — System Operations |
**Group:** Execution Control |
**Forms:** 10 |
**Unique mnemonics:** 10
Architectural control, EBREAK, ASSERT, ACR operations.
Instructions¶
| Mnemonic | Assembly | Length | Decode | Description |
|---|---|---|---|---|
| ACRC | acrc rst_type |
32 | — | Architectural control (ring call). Calls an implementation-defined ACR. |
| ACRE | acre rra_type |
32 | — | Architectural control (ring entry). Enters an implementation-defined ACR. |
| ASSERT | assert SrcL |
32 | — | Architectural assertion. Traps if the condition register is zero. |
| BSE | bse SrcL |
32 | — | Execution control instruction. |
| BWE | bwe SrcL |
32 | — | Execution control instruction. |
| BWI | bwi SrcL |
32 | — | Execution control instruction. |
| BWT | bwt SrcL |
32 | — | Execution control instruction. |
| EBREAK | ebreak imm |
32 | — | Environment break instruction. Traps to the debugging or OS handler. |
| FENCE.D | fence.d pred_imm, succ_imm |
32 | — | Data memory ordering fence. |
| FENCE.I | fence.i |
32 | — | Instruction-cache fence. Synchronizes instruction fetch with prior stores. |