ASSERT

32-bit Base **Group:** Execution Control  |  Ch 19   SYS — System Operations  |  **Length:** 32  |  **Decode:** —

Assembly Syntax

• assert SrcL

Encoding

Bitfield encoding diagram. MSB is on the left, LSB on the right.

Description

Architectural assertion. Traps if the condition register is zero.

Pseudocode (informative)

Trap(EBREAK);

Encoding Notes

No additional encoding notes.

Full Catalog Forms

Assembly	Length	Decode
assert SrcL	32	—

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