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V.SLL

64-bit V. **Group:** Arithmetic Operation  |  Ch 12   ALU — Arithmetic Logic Unit  |  **Length:** 64  |  **Decode:** —

Assembly Syntax

  • v.sll SrcL, SrcR, ->Dst

Encoding

V.SLL encoding
Bitfield encoding diagram. MSB is on the left, LSB on the right.

Description

[64-bit V.] Logical left shift.

Pseudocode (informative)

rd = rs1 << (rs2 & 63);

Encoding Notes

No additional encoding notes.

Full Catalog Forms

Assembly Length Decode
v.sll SrcL, SrcR, ->Dst 64 —
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