V.REM

64-bit V. **Group:** Division  |  Ch 20   VEC — Vector / SIMD Execution (lx64)  |  **Length:** 64  |  **Decode:** —

Assembly Syntax

• v.rem SrcL, SrcR, ->Dst

Encoding

Bitfield encoding diagram. MSB is on the left, LSB on the right.

Description

[64-bit V.] Signed integer remainder.

Pseudocode (informative)

rd = (rs2 != 0) ? (rs1 % rs2) : rs1;

Encoding Notes

No additional encoding notes.

Full Catalog Forms

Assembly	Length	Decode
v.rem SrcL, SrcR, ->Dst	64	—

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