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V.LWU

64-bit V. **Group:** Load Register Offset  |  Ch 11   AGU — Address Generation Unit  |  **Length:** 64  |  **Decode:** —

Assembly Syntax

  • v.lwu<.local> [SrcL, <lc0<<2>, SrcR<<<shamt>], ->Dst

Encoding

V.LWU encoding
Bitfield encoding diagram. MSB is on the left, LSB on the right.

Description

[64-bit V.] Loads a 32-bit value from memory.

Pseudocode (informative)

rd = Load(/* addr */);

Encoding Notes

No additional encoding notes.

Full Catalog Forms

Assembly Length Decode
v.lwu<.local> [SrcL, <lc0<<2>, SrcR<<<shamt>], ->Dst 64 —
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