V.CSEL

64-bit V. **Group:** Three Source Integer  |  Ch 20   VEC — Vector / SIMD Execution (lx64)  |  **Length:** 64  |  **Decode:** —

Assembly Syntax

• v.csel SrcP, SrcL, SrcR<.neg>, ->Dst

Encoding

Bitfield encoding diagram. MSB is on the left, LSB on the right.

Description

[64-bit V.] Conditional select.

Pseudocode (informative)

rd = (rs_p != 0) ? rs1 : rs2;

Encoding Notes

No additional encoding notes.

Full Catalog Forms

Assembly	Length	Decode
v.csel SrcP, SrcL, SrcR<.neg>, ->Dst	64	—

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