V.ADD

64-bit V. **Group:** Arithmetic Operation  |  Ch 12   ALU — Arithmetic Logic Unit  |  **Length:** 64  |  **Decode:** —

Assembly Syntax

• v.add SrcL, SrcR<.neg><<<shamt>, ->Dst

Encoding

Bitfield encoding diagram. MSB is on the left, LSB on the right.

Description

[64-bit V.] Integer addition.

Pseudocode (informative)

rd = rs1 + rs2;

Encoding Notes

No additional encoding notes.

Full Catalog Forms

Assembly	Length	Decode
v.add SrcL, SrcR<.neg><<<shamt>, ->Dst	64	—

← [Arithmetic Operation](../groups/arithmetic_operation.md)    [Index](../index.md)    [All instructions](index.md) →