LD

32-bit Base **Group:** Load Register Offset  |  Ch 11   AGU — Address Generation Unit  |  **Length:** 32  |  **Decode:** —

Assembly Syntax

• ld [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd}

Encoding

Bitfield encoding diagram. MSB is on the left, LSB on the right.

Description

Loads a 64-bit value from memory.

Pseudocode (informative)

rd = Load(/* addr */);

Encoding Notes

No additional encoding notes.

Full Catalog Forms

Assembly	Length	Decode
ld [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd}	32	—

← [Load Register Offset](../groups/load_register_offset.md)    [Index](../index.md)    [All instructions](index.md) →