FEQS

32-bit Base **Group:** Floating-point Compare  |  Ch 13   FSU — Floating-point / SIMD Unit  |  **Length:** 32  |  **Decode:** —

Assembly Syntax

• feqs.{T} SrcL, SrcR, ->{t, u, Rd}

Encoding

Bitfield encoding diagram. MSB is on the left, LSB on the right.

Description

Instruction from the Floating-point Compare group.

Pseudocode (informative)

rd = (fs1 == fs2) ? 1 : 0;

Encoding Notes

No additional encoding notes.

Full Catalog Forms

Assembly	Length	Decode
feqs.{T} SrcL, SrcR, ->{t, u, Rd}	32	—

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