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Two-Source Floating Point

Ch 20   VEC — Vector / SIMD Execution (lx64)  |  **Group:** Two-Source Floating Point  |  **Forms:** 12  |  **Unique mnemonics:** 12

Two-source floating-point operations.

Instructions

Mnemonic Assembly Length Decode Description
V.FEQ v.feq SrcL, SrcR, ->Dst 64 [64-bit V.] Instruction from the Two-Source Floating Point group.
V.FEQS v.feqs SrcL, SrcR, ->Dst 64 [64-bit V.] Instruction from the Two-Source Floating Point group.
V.FGE v.fge SrcL, SrcR, ->Dst 64 [64-bit V.] Instruction from the Two-Source Floating Point group.
V.FGES v.fges SrcL, SrcR, ->Dst 64 [64-bit V.] Instruction from the Two-Source Floating Point group.
V.FLT v.flt SrcL, SrcR, ->Dst 64 [64-bit V.] Instruction from the Two-Source Floating Point group.
V.FLTS v.flts SrcL, SrcR, ->Dst 64 [64-bit V.] Instruction from the Two-Source Floating Point group.
V.FMAX v.fmax SrcL, SrcR, ->Dst 64 [64-bit V.] Instruction from the Two-Source Floating Point group.
V.FMIN v.fmin SrcL, SrcR, ->Dst 64 [64-bit V.] Instruction from the Two-Source Floating Point group.
V.FNE v.fne SrcL, SrcR, ->Dst 64 [64-bit V.] Instruction from the Two-Source Floating Point group.
V.FNES v.fnes SrcL, SrcR, ->Dst 64 [64-bit V.] Instruction from the Two-Source Floating Point group.
V.MAX v.max SrcL, SrcR, ->Dst 64 [64-bit V.] Instruction from the Two-Source Floating Point group.
V.MIN v.min SrcL, SrcR, ->Dst 64 [64-bit V.] Instruction from the Two-Source Floating Point group.

See Also