Store Pre-Index¶
Ch 11
AGU — Address Generation Unit |
**Group:** Store Pre-Index |
**Forms:** 14 |
**Unique mnemonics:** 14
Store with pre-index writeback.
Instructions¶
| Mnemonic | Assembly | Length | Decode | Description |
|---|---|---|---|---|
| HL.SB.PR | hl.sb.pr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SBI.PR | hl.sbi.pr SrcD, [SrcR, simm], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SD.PR | hl.sd.pr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<3], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SD.UPR | hl.sd.upr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SDI.PR | hl.sdi.pr SrcD, [SrcR, simm], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SDI.UPR | hl.sdi.upr SrcD, [SrcR, simm], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SH.PR | hl.sh.pr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<1], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SH.UPR | hl.sh.upr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SHI.PR | hl.shi.pr SrcD, [SrcR, simm], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SHI.UPR | hl.shi.upr SrcD, [SrcR, simm], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SW.PR | hl.sw.pr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<2], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SW.UPR | hl.sw.upr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SWI.PR | hl.swi.pr SrcD, [SrcR, simm], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SWI.UPR | hl.swi.upr SrcD, [SrcR, simm], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |