Store Post-Index¶
Ch 11
AGU — Address Generation Unit |
**Group:** Store Post-Index |
**Forms:** 14 |
**Unique mnemonics:** 14
Store with post-index writeback.
Instructions¶
| Mnemonic | Assembly | Length | Decode | Description |
|---|---|---|---|---|
| HL.SB.PO | hl.sb.po SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SBI.PO | hl.sbi.po SrcD, [SrcR, simm], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SD.PO | hl.sd.po SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<3], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SD.UPO | hl.sd.upo SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SDI.PO | hl.sdi.po SrcD, [SrcR, simm], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SDI.UPO | hl.sdi.upo SrcD, [SrcR, simm], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SH.PO | hl.sh.po SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<1], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SH.UPO | hl.sh.upo SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SHI.PO | hl.shi.po SrcD, [SrcR, simm], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SHI.UPO | hl.shi.upo SrcD, [SrcR, simm], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SW.PO | hl.sw.po SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<2], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SW.UPO | hl.sw.upo SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SWI.PO | hl.swi.po SrcD, [SrcR, simm], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |
| HL.SWI.UPO | hl.swi.upo SrcD, [SrcR, simm], ->{t, u, Rd} |
48 | — | [48-bit HL.] Stores a register value to memory. |