Store Offset¶
Ch 11
AGU — Address Generation Unit |
**Group:** Store Offset |
**Forms:** 14 |
**Unique mnemonics:** 14
Store instructions with register offsets.
Instructions¶
| Mnemonic | Assembly | Length | Decode | Description |
|---|---|---|---|---|
| V.SBI | v.sbi<.local> SrcL, [SrcR, <lc0>, simm] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SBI.BRG | v.sbi.brg<.local> SrcL, [SrcR, <lc0>, simm] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SDI | v.sdi<.local> SrcL, [SrcR, <lc0<3>, simm] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SDI.BRG | v.sdi.brg<.local> SrcL, [SrcR, <lc0<<3>, simm] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SDI.U | v.sdi.u<.local> SrcL, [SrcR, <lc0<<3>, simm] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SDI.U.BRG | v.sdi.u.brg<.local> SrcL, [SrcR, <lc0<<3>, simm] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SHI | v.shi<.local> SrcL, [SrcR, <lc0<<1>, simm] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SHI.BRG | v.shi.brg<.local> SrcL, [SrcR, <lc0<<1>, simm] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SHI.U | v.shi.u<.local> SrcL, [SrcR, <lc0<<1>, simm] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SHI.U.BRG | v.shi.u.brg<.local> SrcL, [SrcR, <lc0<<1>, simm] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SWI | v.swi<.local> SrcL, [SrcR, <lc0<<2>, simm] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SWI.BRG | v.swi.brg<.local> SrcL, [SrcR, <lc0<<2>, simm] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SWI.U | v.swi.u<.local> SrcL, [SrcR, <lc0<<2>, simm] |
64 | — | [64-bit V.] Stores a register value to memory. |
| V.SWI.U.BRG | v.swi.u.brg<.local> SrcL, [SrcR, <lc0<<2>, simm] |
64 | — | [64-bit V.] Stores a register value to memory. |